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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
256K and 512K Pipelined BurstRAMTM Sedcondary Cache Module for PentiumTM
The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor in conjunction with Intel's Triton chip set. The modules are configured as 32K x 64 and 64K x 64 bits in a 160 pin card edge memory module. Each module uses four of Motorola's 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the BurstRAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0, CLK1) input. Eight write enables are provided for byte write control. PD0 - PD4 map into the Triton chip set for auto-configuration of the cache control. Module family pinout supports 5 V and 3.3 V components. It is recommended that all power supplies be connected. These cache modules are plug and pin compatible with the MCM64AF32SG15, a 256K byte asynchronous module also designed for the Pentium microprocessor in conjunction with Intel's Triton chip set. * Pentium-Style Burst Counter on Chip * Pipelined Data Out * 160 Pin Card Edge Module * Address Pipeline Supported by ADSP Disabled with Ex * All Cache Data and Tag I/Os are TTL Compatible * Three State Outputs * Byte Write Capability * Fast Module Clock Rates: 66 MHz * Fast SRAM Access Times:15 ns for Tag RAM 9 ns for Data RAMs * Decoupling Capacitors for Each Fast Static RAM * High Quality Multi-Layer FR4 PWB with Separate Power and Ground Planes * I/Os are 3.3 V Compatible on Data RAMs * Burndy Connector, Part Number: CELP2X80SC3Z48 * Series 20 Resistors for Noise Immunity
BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp.
MCM72JG32 MCM72JG64
160-LEAD CARD EDGE CASE 1113A-01 TOP VIEW 1
42 43
80
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice. REV 1 5/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM72JG32*MCM72JG64 1
PIN ASSIGNMENT 160-PIN CARD EDGE MODULE TOP VIEW
PRESENCE DETECT TABLE
Cache Size and Functionality 256K Async 512K Async 256K Burst 256K Pipe Burst 512K Burst 512K Pipe Burst 512K 2-Bank Burst Module MCM64AF32 -- -- MCM72JG32 -- MCM72JG64 -- PD4 VSS VSS VSS VSS VSS VSS VSS PD3 NC VSS NC NC VSS VSS VSS PD2 VSS NC VSS VSS NC NC NC PD1 VSS VSS NC NC NC NC VSS PD0 NC NC VSS NC VSS NC VSS
VSS TIO1 TIO7 TIO5 TIO3 (RSVD) NC VCC5 (RSVD) NC *(CAA4) CADV VSS COE CWE5 CWE7 CWE1 VCC5 CWE3 *(CAB3) NC *(CALE) NC VSS (RSVD) NC A4 A6 A8 A10 VCC5 A17 VSS A9 A14 A15 (RSVD) NC PD0 PD2 PD4 VSS CLK0 VSS DQ63 VCC5 DQ61 DQ59 DQ57 VSS DQ55 DQ53 DQ51 DQ49 VSS DQ47 DQ45 DQ43 VCC5 DQ41 DQ39 DQ37 VSS DQ35 DQ33 DQ31 VCC5 DQ29 DQ27 DQ25 VSS DQ23 DQ21 DQ19 VCC5 DQ17 DQ15 DQ13 VSS DQ11 DQ9 DQ7 VCC5 DQ5 DQ3 DQ1 VSS
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VSS TIO0 TIO2 TIO6 TIO4 NC (RSVD) VCC3 TWE CADS (CAA3)* VSS CWE4 CWE6 CWE0 CWE2 VCC3 CCS (CAB4)* NC (GWE)** NC (BWE)** VSS A3 A7 A5 A11 A16 VCC3 NC (A18){ VSS A12 A13 ADSP NC (ECS1, CS) NC (ECS2) PD1 PD3 VSS CLK1 VSS DQ62 VCC3 DQ60 DQ58 DQ56 VSS DQ54 DQ52 DQ50 DQ48 VSS DQ46 DQ44 DQ42 VCC3 DQ40 DQ38 DQ36 VSS DQ34 DQ32 DQ30 VCC3 DQ28 DQ26 DQ24 VSS DQ22 DQ20 DQ18 VCC3 DQ16 DQ14 DQ12 VSS DQ10 DQ8 DQ6 VCC3 DQ4 DQ2 DQ0 VSS
PIN NAMES
A3 - A18 . . . . . . . . . . . . . . . . . . . . . Cache Address DQ0 - DQ63 . . . . . . . . . . . . . . . . Data Input/Output CLK0, CLK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock CWE0 - CWE7 . . . . . . . . . . . Cache Write Enable BWE** . . . . . . . . . . . . . . . . . . . . . Byte Write Enable GWE** . . . . . . . . . . . . . . . . . . . Global Write Enable TIO0 - TIO7 . . . . . . . . . . . . . . . . . Tag Input/Output TWE . . . . . . . . . . . . . . . . . . . . . . . . Tag Write Enable CADS . . . . . . . . . . . . . . . . . Cache Address Status ADSP . . . . . . . . . . . . . . . Address Status Processor CADV . . . . . . . . . . . . . . . . . . Cache Burst Advance COE . . . . . . . . . . . . . . . . . . . . Cache Output Enable CCS . . . . . . . . . . . . . . . . . . . . . . . Cache Chip Select RSVD . . . . . . . . . . . . . . . Reserved for Future Use PD0 - PD4 . . . . . . . . . . . . . . . . . . Presence Detect VCC5 . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VCC3 . . . . . . . . . . . . . . . . . . . + 3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connect
NOTES: * Signals in parentheses indicate pin descriptions for asynchronous Triton chip set module. ** Signals in parentheses will be implemented in future burstable Triton modules. { NC for MCM72JG32, A18 for MCM72JG64.
MCM72JG32*MCM72JG64 2
MOTOROLA FAST SRAM
MCM72JG32 MODULE BLOCK DIAGRAM
32K x 8 TIO0 - TIO7 TWE 13 A5 - A17 DQ0 - DQ7 W A0 - A12 E A13 A14 G
A18 - NC A3 - A17 ADSP CADS CADV CLK0 COE CCS 15
MCM67J518 A0 - A14 ADSP ADSC ADV K G E LW DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 CWE1 DQ8- DQ15 8 CWE0 DQ0 - DQ7
MCM67J518 A0 - A14 ADSP ADSC ADV K G E LW DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 CWE3 DQ24- DQ31 8 CWE2 DQ16 - DQ23
MCM67J518 A0 - A14 ADSP ADSC ADV CLK1 K G E LW DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 CWE5 DQ40- DQ47 8 CWE4 DQ32 - DQ39
MCM67J518 A0 - A14 ADSP ADSC ADV K G E PD0 - NC PD1 - NC PD2 PD3 - NC PD4 LW DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 CWE7 DQ56- DQ63 8 CWE6 DQ48 - DQ55
MOTOROLA FAST SRAM
MCM72JG32*MCM72JG64 3
MCM72JG64 MODULE BLOCK DIAGRAM
32K x 8 TIO0 - TIO7 TWE 14 A5 - A18 DQ0 - DQ7 W A0 - A13 E A14 G
MCM67J618 A3 - A18 ADSP CADS CADV CLK0 COE CCS 16 A0 - A15 ADSP ADSC ADV K G E LW DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 CWE1 DQ8- DQ15 8 CWE0 DQ0 - DQ7
MCM67J618 A0 - A15 ADSP ADSC ADV K G E LW DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 CWE3 DQ23- DQ31 8 CWE2 DQ16 - DQ23
MCM67J618 A0 - A15 ADSP ADSC ADV CLK1 K G E LW DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 CWE5 DQ40- DQ47 8 CWE4 DQ32 - DQ39
MCM67J618 A0 - A15 ADSP ADSC ADV K G E PD0 - NC PD1 - NC PD2 - NC PD3 PD4 LW DQ0 - DQ7 DQ8 UW DQ9 - DQ16 DQ17 8 CWE7 DQ56- DQ63 8 CWE6 DQ48 - DQ55
MCM72JG32*MCM72JG64 4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
160-Lead Card Edge Pin Locations 20, 21, 22, 23, 24, 28, 29, 101, 102, 103, 104, 106, 108, 109, 110 36, 116 11, 12, 13, 14, 92, 93, 94, 96 8 -- -- 16 30 Symbol A3 - A18 CLK0, CLK1 CWE0 - CWE7 TWE BWE GWE CCS ADSP Type Input Input Input Input Input Input Input Input Description Address Inputs: These inputs are registered into data RAMs and must meet setup and hold times. The tag RAM addresses are not registered. Clock: This signal registers the address, data in, and all control signals except COE. Cache Data Byte Write Enable: Active low write signal for data RAMs. Tag Write Enable: Active low write signal for tag RAMs. Byte Write Enable: To be used in future modules. Global Write Enable: To be used in future modules. Chip Select: Active low chip enable for data RAMs. Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (Exception-chip deselect does not occur when ADSP is asserted and CCS is high. Cache Address Status: Initiates READ, WRITE, or chip deselect cycle. Cache Burst Advance: Increments address count in accordance with interleaved count style. Cache Output Enable: Active low asynchronous input. Low-enables output buffers (DQ pins) High-DQx pins are high impedance. Synchronous Data I/O: Drives data out of data RAMs during READ cycles. Stores data to data RAMs during WRITE cycles.
9 89 91
CADS CADV COE
Input Input Input
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66, 67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120, 121, 122, 124, 125, 126, 127, 129, 130, 131, 133, 134, 135, 137, 138, 139, 141, 142, 143, 145, 146, 147, 149, 150, 151, 153, 154, 155, 157, 158, 159 2, 3, 4, 5, 82, 83, 84, 85
DQ0 - DQ63
I/O
TIO0 - TIO7 PD0 - PD4 VCC3 VCC5 VSS
I/O
Tag RAM I/O: Drives data out during tag compare cycles. Stores data to tag RAM during tag WRITE cycles. Presence Detect: See Presence Detect Table Power Supply: 3.3 V 5%. Power Supply: 5.0 V 5%. Ground
33, 34, 112, 113, 114 7, 15, 25, 39, 52, 60, 68, 76 87, 95, 105, 119, 132, 140, 148, 156 1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72, 80, 81, 90, 99, 107, 115, 117, 123, 128, 136, 144, 152, 160 6, 17, 18, 26, 31, 32, 86, 88, 97, 98, 100, 111
-- Supply Supply Supply
NC
--
No Connection: There is no connection to the module.
MOTOROLA FAST SRAM
MCM72JG32*MCM72JG64 5
64K x 18 BurstRAM BLOCK DIAGRAM (See Note)
ADV BURST LOGIC Q0 CLK BINARY COUNTER Q1 ADSC CLR A1 A0 16 A1 64K x 18 MEMORY ARRAY INTERNAL A0 ADDRESS
ADSP A0 - A15 ADDRESS REGISTER 16 A1 - A0
2 A2 - A15 18 9 9
UW LW
WRITE REGISTER
DATA-IN REGISTERS
E
ENABLE REGISTER
9
9
DATA-OUT REGISTERS OUTPUT BUFFER
G DQ0 - DQ8 DQ9 - DQ17 9 9
NOTE: All registers are positive-edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of CWE and ADSC) is performed using the new external address. Alternatively, an ADSP-initiated two cycle WRITE can be performed by negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write cycle in WRITE CYCLES timing diagram). When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on CWE) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
64K x 18 BURST SEQUENCE TABLE (See Note)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A15 - A2 A15 - A2 A15 - A2 A15 - A2 A1 A1 A1 A1 A0 A0 A0 A0
NOTE: The burst wraps around to its initial state upon completion.
NOTE: The above BurstRAM Block Diagram and Burst Sequence Table apply specifically tothe 64K x 18 chip. The 32K x 18 chip is functionally identical but has no A15.
MCM72JG32*MCM72JG64 6
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
CCS H L L L X X X X H H H H ADSP X L H H H H H H X X X X CADS L X L L H H H H H H H H CADV X X X X L L H H L L H H CWEx X X L H L H L H L H L H CLK0/1 L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Address Used N/A External Address External Address External Address Next Address Next Address Current Address Current Address Next Address Next Address Current Address Current Address Operation Deselected Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means Don't Care. 2. All inputs except COE must meet setup and hold times for the low-to-high transition of clock (CLK0/1). 3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Read Write Deselected COE L H X X I/O Status Data Out High-Z High-Z -- Data In High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Temperature Under Bias Operating Temperature Storage Temperature Symbol VCC5 Vin, Vout Iout Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 - 10 to + 85 0 to +70 Unit V V mA C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MOTOROLA FAST SRAM
MCM72JG32*MCM72JG64 7
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.75 2.2 - 0.5* Max 5.25 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (COE = VIH) TTL Output Low Voltage (IOL = + 8.0 mA) TTL Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 3.3 Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Supply Current (COE = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) AC Standby Current (COE = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) Symbol ICCA ISB1 Max 1300 340 Unit mA mA
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input Capacitance Input/Output Capacitance (Address and Control) (CLK0, CLK1) (DQ0 - DQ63) Symbol Cin Cin CI/O Max 28 12 10 Unit pF pF pF
MCM72JG32*MCM72JG64 8
MOTOROLA FAST SRAM
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5% TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM72JG32-66 MCM72JG64-66 Parameter Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Address Address Status Data In Write Address Advance Chip Enable Address Address Status Data In Write Address Advance Chip Enable Symbol tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX Min 15 -- -- 2 2 1 -- 2 5 5 2.5 Max -- 7 5 -- -- -- 6 6 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 7 6 5 Notes
Hold Times:
0.5
--
ns
7
NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP high for the setup and hold times. 3. All read and write cycle timings are referenced from CLK or COE. 4. COE is a don't care when UW or LW is sampled low. 5. Maximum access times are guaranteed for all possible i486 amd Pentium external bus cycles. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever ADSP or CADS is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP or CADS is low) to remain enabled.
MOTOROLA FAST SRAM
MCM72JG32*MCM72JG64 9
DATA RAMs READ CYCLES
t KHKH
CLK0, CLK1 t KLKH t KHKL
t ADSVKH
t KHADSX
MCM72JG32*MCM72JG64 10
t AVKH t ADSVKH A2 A3 ADSP STARTS NEW BURST t KHADSX t EVKH t KMWX t WVKH t ADWKH t KHADVX ADSP blocked with E high, ADDR ignored t GLQX (CADV SUSPENDS BURST) t GHQZ t KHQX2 Q(A1) SINGLE READ t KHQV Q(A2) Q(A2+1) Q (A2+2) BURST READ Q(A2+3) (BURST WRAPS AROUND TO ITS INITIAL STATE) Q (A2) Q (A3) Q(A3+1) BURST READ Q(A3+2)
ADSP
CADS
t KNAX
Ax (Address)
A1
CWEx
t KHEX
CCS
CADV
COE
t KHQV
t KHQX1
MOTOROLA FAST SRAM
DQ
DATA RAMs WRITE CYCLES
t KHKH
CLK0, CLK1 t KHKL t KHADSX t KLKH
t ADSVKH
MOTOROLA FAST SRAM
t ADSVKH t KHADSX CADS STARTS NEW BURST t KHAX A1 W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST A2 A3 t WVKH t KHEX t ADVVKH CADV SUSPENDS BURST t DVKH D(A1) t GHQZ D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) SINGLE WRITE BURST WRITE (WITH A SUSPENDED CYCLE) NEW BURST WRITE
ADSP
CADS
t AVKH
Ax (Address)
t KHWX
CWEx
t EVKH
CCS t KHADVX
CADV
COE t KHDX
DATA IN
D(A3 + 2)
DATA OUT
Q(An - 1)
Q(An)
MCM72JG32*MCM72JG64 11
BURST READ
DATA RAMs COMBINATION READ/WRITE CYCLES (CCS low, CADS high)
t KHKH
CLK0, CLK1 t KLKH t KHKL
t KHADSX
MCM72JG32*MCM72JG64 12
A1 t KHWX t WVKH A2 A3 t KHADVX t ADVKH t KHDX t DVKH D(A2) t KHQV t GHQZ Q(A1) t GLQX t KHQV t KHQX2 Q(A3) Q(A3 + 1) Q(A3 + 2) READ WRITE BURST READ
t ADVSKH
ADSP
t AVKH t KHAX
Ax (Address)
CWEx
CADV
COE
D
t KHQX1
MOTOROLA FAST SRAM
Q
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
TAG RAM READ CYCLE (See Note 1 and 5)
- 15 Parameter Read Cycle Time Address Access Time Output Hold from Address Change Symbol tAVAV tAVQV tAXQX Min 15 -- 4 Max -- 15 -- Unit ns ns ns 3, 4 Notes 2
NOTES: 1. CWE is high for read cycle. 2. All timings are referenced from the last valid address to the first address transition. 3. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 4. This parameter is sampled and not 100% tested. 5. Device is continuously selected (COE = VIL).
TAG RAM READ CYCLE (See Note 5)
tAVAV Ax (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
MOTOROLA FAST SRAM
MCM72JG32*MCM72JG64 13
TAG RAM WRITE CYCLE (See Notes 1 and 2)
- 15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Data Valid to End of Write Data Hold Time Write Low to Output High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 15 0 12 7 0 0 4 0 Max -- -- -- -- -- 7 -- -- Unit ns ns ns ns ns ns ns ns 5,6,7 5,6,7 Notes 3
NOTES: 1. A write occurs when CWE is low. 2. If COE goes low coincident with or after CWE goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first address transition. 4. If COE VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 2B. 7. This parameter is sampled and not 100% tested.
TAG RAM WRITE CYCLE (See Notes 1 and 2)
tAVAV AX (ADDRESS) tAVWH tWLWH TWE tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH Z HIGH Z tDVWH DATA VALID tWHQX tWHDX tWHAX
AC TEST LOADS
+5 V Z0 = 50 OUTPUT 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MCM72JG32*MCM72JG64 14
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
72JG32 72JG64
XX
XX
Speed (66 = 66 MHz) Package (SG = Gold Pad SIMM)
Full Part Numbers -- MCM72JG32SG66
MCM72JG64SG66
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM72JG32*MCM72JG64 15
PACKAGE DIMENSIONS
160-LEAD CARD EDGE MODULE CASE 1113A-01 A E
COMPONENT AREA
C
NOTE 4
B
-Y- VIEW AA
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM72JG32*MCM72JG64 16
EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E
FULL R 80 43 42 1 2X
P
V
NOTE 4
F
AC
-X-
L
M
AB
NOTE 5
J -T- SIDE VIEW
NOTE 6
FRONT VIEW
0.012 (0.3)
M
R
R
W
(N)
EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE
160
EEE E E EEE E E EEE E E EEE E E EEE E E
VIEW AA
123 122
160X
D 0.004 (0.1)
L
TYX
S
160X
H
160X
K
156X
G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND V DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION AB DEFINES OPTIONAL SINGLE-SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. DIM A B C D E F G H J K L M N P R V W AB AC INCHES MIN MAX 4.330 4.350 1.270 1.310 --- 0.454 0.033 0.037 2.265 2.275 0.075 BSC 0.050 BSC --- 0.030 0.055 0.069 0.210 --- 1.955 1.965 2.155 2.165 0.110 REF 0.125 --- 0.285 0.305 0.157 --- 0.040 0.060 --- 0.262 0.072 0.076 MILLIMETERS MIN MAX 109.98 110.49 32.26 33.27 --- 11.53 0.84 0.94 57.53 57.79 1.91 BSC 1.27 BSC --- 0.51 1.40 1.75 5.33 --- 49.66 49.91 54.74 54.99 2.79 REF 3.18 --- 7.24 7.75 3.99 --- 1.02 1.52 --- 6.66 1.83 1.93
81
COMPONENT AREA
BACK VIEW
*MCM72JG32/D*
MOTOROLA MCM72JG32/D FAST SRAM

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